Programmable circuit and its method of operation

ABSTRACT

A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold voltage values for operation. During reading of the transistor, a gate threshold voltage between the two values is applied and the status of the transistor as on or off is determined to determine the program state of the transistor. The program state of the transistor can be determined by a simple latch circuit.

[0001] One of the ways to implement a programmable feature on anintegrated circuit is by utilizing fuses or antifuses. Fuses areselectively electrically programmed by applying a program voltage whichopens a circuit between two conductive terminals of the fuse. For laserfuses, a laser is used to cut a fuse link. An antifuse is electricallyprogrammed by applying a programming voltage to break down dielectricmaterial connected to two conductive terminals of the antifuse.

[0002] The programming voltage permanently changes either the fuse orantifuse to provide a high or low resistance in accordance with theprogramming. In the case of an antifuse, the high resistance istypically a program resistance on the order of hundreds of thousandohms.

[0003] The programming voltage for a fuse or antifuse is typically quitehigh, for example, over 8 volts. This high voltage must be routed toselective fuse or antifuse elements on an integrated circuitry withoutaffecting other highly sensitive lower voltage signal paths.Accordingly, the introduction of high fuse or antifuse programmingvoltages requires careful design and process modifications, such astailored junction profiles or thick gate oxides in order to avoid damageto other sensitive components on the integrated circuit die. Thisincreases fabrication complexity as well as chip size.

[0004] A programmable circuit which relies on a lower programmingvoltage and decreased die area for the programmable element would bedesirable.

[0005] Also, in the testing of DRAM memory devices utilizing boostedwordline voltages, a Vt shift of several hundred millivolts hasinadvertently been produced in small n-channel transistors in the memoryarray. This causes the affected memory cells to be inferior since thedata to be stored in the cell is not as readily transferred through theaffected n-channel access device. To avoid this detrimental effect,device manufacturing processes have been modified. This inventionutilizes this effect which is detrimental to the memory array, for animproved programmable circuit element outside of the memory array.

SUMMARY OF THE INVENTION

[0006] The present invention provides a programmable circuit whichrelies on a programmable transistor in which the gate threshold voltagefor turning the transistor on is programmable. The gate thresholdvoltage may be programmed to be either a first voltage or a secondvoltage. The program state of the transistor can be determined byapplying a gate threshold voltage between the first and second gatethreshold voltages and then determining the operative state, i.e.; on oroff, of the transistor.

[0007] One of the first and second gate threshold voltages for thetransistor can be selected as the normal gate threshold operatingvoltage for the transistor, while the other gate threshold voltage canbe set by applying suitable voltages to the gate and drain electrodes ofthe transistor to thereby alter the gate threshold voltage to a secondvalue away from the normal gate threshold voltage. The programmingvoltage for the gate and drain are lower than voltage typically used toprogram a fuse or antifuse element.

[0008] The programming circuit of the invention has particular utilityin any integrated circuit which requires a programmable element and hasparticular utility in the field of DRAMs as a replacement for a fuse orantifuse element.

[0009] The above advantages and features of the invention will be moreclearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 illustrates a programmable circuit in an exemplaryembodiment of the invention;

[0011]FIG. 2 illustrates signal sources for providing the operativesignals for the FIG. 1 circuit; and

[0012]FIG. 3 illustrates a processor circuit which employs a memorydevice using the FIG. 1 circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] An exemplary embodiment of the invention is illustrated in FIGS.1 and 2. FIG. 1 illustrates a programmable transistor 70 illustrated asan n-channel transistor which has its gate coupled to a programmingsignal line VPRGG 100 and its drain coupled to another programmingsignal line VPRGD 90. As fabricated, transistor 70 has a normal gateoperating threshold voltage Vt, e.g. 0.7 v. The gate threshold operatingvoltage Vt can be changed by programming on the signal lines 90 and 100.For example, if the normal gate threshold Vt for transistor 70 is 0.7 v,the application of a programming voltage on the signal lines 90 and 100to the drain and gate terminals respectively can change this thresholdvoltage Vt to another higher value, e.g. 1.5 v.

[0014] If, for example, 6 volts is applied to the gate via signal line100, and 4.5 volts is applied to the drain via signal line 90, and asubstrate bias voltage Vbb in which the circuit of FIG. 1 is fabricatedis lowered from a value in the range of −0.6 to −1.0 volts, to a valueof −2.0 volts, and this condition is maintained for approximately 5seconds, the threshold voltage Vt of transistor 70 will permanentlyshift to approximately 1.5 volts. It is thought that this shift inthreshold voltage is caused by charges being trapped in the gate oftransistor 70 by the noted programming conditions. Accordingly, the gatethreshold voltage of transistor 70 can remain at the original thresholdvoltage level Vt or can be programmed to a different substantiallyhigher voltage level, e.g., approximately 2 Vt, thus establishing twopossible gate threshold voltages for transistor 70.

[0015] The programmed state of programmable transistor 70, that is,whether it is operating with the initial gate threshold voltage Vt orwith a substantially higher gate threshold voltage, can be determined bygrounding line 90 and applying a gate threshold voltage on line 100,which is between the normal threshold voltage Vt and the higher gatethreshold voltage, and then determining whether the transistor 70 is“on” or “off.” If the transistor 70 was set at its normal voltagethreshold Vt, a higher voltage threshold applied to the gate oftransistor 70 on line 100 will cause transistor 70 to turn “on.”.Likewise, if the voltage threshold for programmable transistor 70 hasbeen changed to a higher value, then when a threshold voltage on line100, which is between the original value Vt and the higher value, isapplied, transistor 70 will remain “off” when line 90 is grounded. Thus,programmable transistor 70 provides a simple and convenient way ofprogramming a programmable element which does not require the samemagnitude of programming voltages as is required with a fuse or antifusedevice.

[0016]FIG. 1 further illustrates a latch circuit 120 which is used todetermine whether transistor 70 is “on” or “off,” thus determining thestate to which transistor 70 was programmed. Latch circuit 120 includesan input node A and an output node B, with the output node B supplying asignal indicating the program state of programmable transistor 70.

[0017] Input node A is connected to the source terminal of transistor70, and an inverter 60 is connected between input node A and output nodeB of latch circuit 120. Latch circuit 120 further includes two p-channeltransistors 20 and 30, with the sources of transistors 20 and 30connected together and the drains of transistors 20 and 30 connectedtogether. The sources of transistors 20 and 30 are, in turn, coupled toa voltage source Vcc through another p-channel transistor 10. The drainsof transistors 20 and 30 are connected to node A.

[0018] Latch circuit 120 also includes two n-channel transistors 50 and40 which are serially connected with the source of transistor 50 beingconnected to the drain of transistor 40, and with the transistors 40 and50 being in turn serially connected between node A and ground. The gatesof transistors 30 and 40 are connected to the output node B, while thegates of transistors 20 and 50 are connected to a read fuse RDFUS* (*denotes an active “low signal” line) signal line 110. Transistor 10 hasits gate connected to a test margin control signal line MRG* 80.

[0019]FIG. 2 illustrates a program voltage source 130 which suppliessignals to the VPRGD and VPRGG signal lines 90 and 100, respectively forprogramming transistor 70, and a read signal source 140 which suppliessignals on the lines VPRGD, VPRGG, MRG* and RDFUS*, that is, to lines90, 100, 80 and 110, respectively.

[0020] The programmable signal source 130 is operative to programtransistor 70 to set the higher threshold voltage as needed or desired.Program voltage source 130 can be resident on an integrated circuitsubstrate containing the FIG. 1 circuit, or may be an external sourcewhich controls application of the programming signals on lines 90 and100 via external terminals of the integrated circuit. Transistor 70 canbe programmed during a testing state of an integrated circuit or, ifexternal terminals of a packaged device are used to control the signalsfor lines 90, 100, by a user of the integrated circuit.

[0021] The read signal source 140 is resident on the integrated circuitcontaining the FIG. 1 circuit and provides the signals VPRGD, VPRGG,MRG* and RDFUS* during a read operation to ascertain the status oftransistor 70. In particular, a gate threshold voltage is applied to theline VPRGG 100, which is between the original gate threshold voltage Vtand the higher threshold voltage which is set when programming signalsare previously applied on lines 90 and 100, as described above. Forexample, if the higher gate threshold is approximately 2 Vt, when theapplied gate threshold voltage during a read operation is between Vt and2 Vt.

[0022] During the time that the gate threshold voltage is applied for aread operation to terminal 100, signal line 90 is grounded and thesignal source 140 also applies the MRG* signal on line 80, which turnson transistor 10 and thereby applies power to the latch circuit 120.Note, MRG* may be set between Vcc minus a p-channel transistor Vt and 0volts during normal operation. In a test mode it is lowered to provide astronger pull up at node A to ensure adequate operating margin for thecircuit. After power is applied, a signal is applied on line RDFUS* 110,which serves to turn on transistor 20 and turn off transistor 50. If atthe time the RDFUS* signal is applied to turn on transistor 20, avoltage Vcc is produced at node A, then transistor 70 is turned “off.”The voltage at node A is inverted by inverter 60 and is applied atoutput node B as a low voltage, e.g., “0” volts.

[0023] On the other hand, if when the RDFUS* signal is applied and turnson transistor 20, transistor 70 is also turned “on” by the gatethreshold voltage VPRGG on line 100 and the grounding of line 90, thenthe Vcc voltage applied at node A will be diverted to ground throughtransistor 70 and the drain of transistor 70 and line 90. Thus, thevoltage at node A will be at a low voltage, e.g., substantially “0”volts which, after inversion by inverter 60, will be seen at node B as ahigh output, e.g., as substantially Vcc.

[0024] When the voltage at terminal A goes to a high voltage andtransistor 70 is off, the high voltage at node A will produce a lowvoltage at node B which is, in turn, supplied to transistor 30, causingit to turn on and hold the voltage at node A at the high voltage, andthe voltage at node B at a low value. The low voltage at node B willmaintain transistor 40 off, and thus the operative state of transistor50 does not affect operation of the latch circuit 120.

[0025] If when transistor 20 is turned on and transistor 50 is turnedoff by the RDFUS* signal on line 110, and if at that time programmabletransistor 70 is turned on, this produce a low voltage at node A which,in turn, produces a high voltage at node B. The high voltage at node Bturns transistor 40 on and transistor 30 off and, when the RDFUS*returns to its normal high state this turns on transistor 50, whichlatches node A at the low voltage which, in turn, latches node B at thehigh voltage.

[0026] Thus, during a read operation, the state of output node B oflatch circuit 120 reflects the operative state of transistor 70, i.e.,“on” or “off,” which in turn reflects the programmed state ofprogrammable transistor 70.

[0027] The application of the read gate threshold voltage VPRGG at alevel between the two possible threshold voltages for transistor 70 canbe done at the same time the RDFUS* signal is applied to line 110.

[0028] The invention provides a simple expedient of a program transistoras a programmable element and a simple latch circuit to determine thestate of the programmable element. The voltages required to program thetransistors are much less than those required to program a fuse orantifuse element.

[0029] The programmable circuit of the invention may be used in anenvironment which requires the use of programmable elements in an analogor digital semiconductor circuit, including but not limited to logiccircuits, processors, other programmable logic circuits, and memorydevices. The invention may particularly be useful in memory devices as aprogrammable element for providing identification codes and/orprogramming to re-map defective memory cell addresses. In particular,DRAM devices where a boosted word line voltage has been known toinadvertantly produce Vf shifts in small n-channel transistors in thememory array. This boosted word line voltage may be used to generateeither or both of the VPRGG and VPRGD signals.

[0030] A processor system which may employ the programmable circuit ofthe invention is illustrated in FIG. 3. As shown in FIG. 3, theprocessor system, such as a computer system, for example, comprises acentral processing unit (CPU) 210, for example, a microprocessor, thatcommunicates with one or more input/output (I/O) devices 240, 250 over abus 270. The computer system 200 also includes random access memory(RAM) 260, a read only memory (ROM) 280 and may include peripheraldevices such as a floppy disk drive 220 and a compact disk (CD) ROMdrive 230 which also communicates with CPU 210 over the bus 270. One ormore of the RAM 260, CPU 210, ROM 280 may be constructed as anintegrated circuit which includes the programmable transistor 70 andlatch circuit 120 as described above. It may also be desirable tointegrate the processor 210 and memory 260 on a single IC chip. Numerousother system configurations are possible which are fullly compatiblewith the present invention.

[0031] Although the invention has been described above in connectionwith exemplary embodiments, it is apparent that many modifications andsubstitutions can be made without departing from the spirit or scope ofthe invention. Accordingly, the invention is not to be considered aslimited by the foregoing description, but is only limited by the scopeof the appended

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A programmable circuit comprising: aprogrammable transistor which is selectively programmable to have itsgate threshold voltage at one of a first gate threshold voltage and asecond threshold voltage; and a read circuit for reading the programstatus of said programmable transistor, said circuit applying voltage tosource and drain terminals of said programmable transistor and a thirdthreshold voltage which is between said first and second thresholdvoltages to a gate of said programmable transistor, said read circuitdetermining the operative state of said programmable transistor whensaid third threshold voltage is applied.
 2. A programmable circuit as inclaim 1 wherein said read circuit comprises: a first circuit portion forapplying said third threshold voltage to said gate during a readoperation; and a second circuit portion for determining the operativestatus of said transistor during said read operation.
 3. A programmablecircuit as in claim 2 wherein said second circuit portion includes alatch having an input node coupled to one of a source and drain terminalof said transistor, the operative state of said transistor determiningthe voltage at said input node and controlling the output state of saidlatch at an output node during said read operation.
 4. A programmablecircuit as in claim 3 wherein said latch comprises an inverter having aninput coupled to said input node and an output coupled to said outputnode.
 5. A programmable circuit as in claim 3 wherein said latch circuitcomprises: an input node for receiving a read signal which renders saidlatch operative to determine the voltage at said input node.
 6. Aprogrammable circuit as in claim 5 wherein said latch circuit furthercomprises: a first and a second transistor, each having a source anddrain terminal, said first and second transistors having their sourceand drain terminal connected in parallel, said first and secondtransistors being connected between a first potential source and saidlatch input node; a third and a fourth transistor, each having a sourceand drain terminal, said third and fourth transistors having theirsource and drain terminals serially connected, said third and fourthtransistors being serially connected between said latch input node and asecond potential source; the gates of said second and fourth transistorsbeing coupled to said output node of said latch and the gates of saidfirst and third transistors being coupled to said read signal line.
 7. Aprogrammable circuit as in claim 6 wherein said first and secondtransistors are p-channel transistors and said third and fourthtransistors are n-channel transistors.
 8. A programmable circuit as inclaim 6 wherein said first and second transistors are coupled to saidfirst potential through a fifth transistor, the gate of said fifthtransistor being coupled to a signal line which receives a controlsignal to control the supply of power from said first power source tosaid latch circuit.
 9. A programmable circuit as in claim 8 furthercomprising a signal generator for generating said control signal atleast during said read operation.
 10. A programmable circuit as in claim1 further comprising: a programming circuit for programming saidprogrammable transistor by applying predetermined voltages to terminalsof said programmable transistor to change said gate threshold voltagefrom one of said first and second gate threshold voltages to the otherof said first and second gate threshold voltages.
 11. A programmablecircuit as in claim 10 wherein said programming circuit applies saidpredetermined voltages to a gate and drain terminals of saidprogrammable transistor.
 12. A programmable circuit as in claim 11wherein said programmable transistor is an n-channel transistor.
 13. Aprogrammable circuit as in claim 1 further comprising: a read signalgenerator for generating a read signal, said read circuit beingresponsive to said read signal for determining the operative state ofsaid programmable transistor.
 14. A programmable circuit as in claim 6further comprising: a read signal generator for generating a read signalon said read signal line.
 15. A programmable circuit as in claim 3wherein a source at said programmable transistor is coupled to saidinput node, and a drain of said programmable transistor is coupled to avoltage potential when said third threshold voltage is applied to saidgate terminal.
 16. A programmable circuit as in claim 1 wherein saidprogrammable circuit is provided in an integrated circuit.
 17. Aprogrammable circuit as in claim 1 wherein said integrated circuit is amemory device.
 18. A memory device comprising: a programmable transistorwhich is selectively programmable to have its gate threshold voltage atone of a first gate threshold voltage and a second threshold voltage;and a read circuit for reading the program status of said programmabletransistor, said circuit applying voltage to source and drain terminalsof said programmable transistor and a third threshold voltage which isbetween said first and second threshold voltages to a gate of saidprogrammable transistor, said read circuit determining the operativestate of said programmable transistor when said third threshold voltageis applied.
 19. A memory device as in claim 18 wherein said read circuitcomprises: a first circuit portion for applying said third thresholdvoltage to said gate during a read operation; and a second circuitportion for determining the operative status of said transistor duringsaid read operation.
 20. A memory device as in claim 19 wherein saidsecond circuit portion includes a latch having an input node coupled toone of a source and drain terminal of said transistor, the operativestate of said transistor determining the voltage at said input node andcontrolling the output state of said latch at an output node during saidread operation.
 21. A memory device as in claim 20 wherein said latchcomprises an inverter having an input coupled to said input node and anoutput coupled to said output node.
 22. A memory device as in claim 20wherein said latch circuit comprises: an input node for receiving a readsignal which renders said latch operative to determine the voltage atsaid input node.
 23. A memory device as in claim 22 wherein said latchcircuit further comprises: a first and a second transistor, each havinga source and drain terminal, said first and second transistors havingtheir source and drain terminal connected in parallel, said first andsecond transistors being connected between a first potential source andsaid latch input node; a third and a fourth transistor, each having asource and drain terminal, said third and fourth transistors havingtheir source and drain terminals serially connected, said third andfourth transistors being serially connected between said latch inputnode and a second potential source; the gates of said second and fourthtransistors being coupled to said output node of said latch and thegates of said first and third transistors being coupled to said readsignal line.
 24. A memory device as in claim 23 wherein said first andsecond transistors are p-channel transistors and said third and fourthtransistors are n-channel transistors.
 25. A memory device as in claim23 wherein said first and second transistors are coupled to said firstpotential through a fifth transistor, the gate of said fifth transistorbeing coupled to a signal line which receives a control signal tocontrol the supply of power from said first power source to said latchcircuit.
 26. A memory device as in claim 25 further comprising a signalgenerator for generating said control signal at least during said readoperation.
 27. A memory device as in claim 18 further comprising: aprogramming circuit for programming said programmable transistor byapplying predetermined voltages to terminals of said programmabletransistor to change said gate threshold voltage from one of said firstand second gate threshold voltages to the other of said first and secondgate threshold voltages.
 28. A memory device as in claim 27 wherein saidprogramming circuit applies said predetermined voltages to a gate anddrain terminals of said programmable transistor.
 29. A memory device asin claim 28 wherein said programmable transistor is an n-channeltransistor.
 30. A memory device as in claim 18 further comprising: aread signal generator for generating a read signal, said read circuitbeing responsive to said read signal for determining the operative stateof said programmable transistor.
 31. A memory device as in claim 23further comprising: a read signal generator for generating a read signalon said read signal line.
 32. A memory device as in claim 20 wherein asource at said programmable transistor is coupled to said input node,and a drain of said programmable transistor is coupled to a voltagepotential when said third threshold voltage is applied to said gateterminal.
 33. A processor system comprising: a processor; and at leastone memory device coupled to said processor, at least one of said memorydevice and processor comprising a programmable circuit, saidprogrammable circuit comprising: a programmable transistor which isselectively programmable to have its gate threshold voltage at one of afirst gate threshold voltage and a second threshold voltage; and a readcircuit for reading the program status of said programmable transistor,said circuit applying voltage to source and drain terminals of saidprogrammable transistor and a third threshold voltage which is betweensaid first and second threshold voltages to a gate of said programmabletransistor, said read circuit determining the operative state of saidprogrammable transistor when said third threshold voltage is applied.34. A system as in claim 33 wherein said read circuit comprises: a firstcircuit portion for applying said third threshold voltage to said gateduring a read operation; and a second circuit portion for determiningthe operative status of said transistor during said read operation. 35.A system as in claim 34 wherein said second circuit portion includes alatch having an input node coupled to one of a source and drain terminalof said transistor, the operative state of said transistor determiningthe voltage at said input node and controlling the output state of saidlatch at an output node during said read operation.
 36. A system as inclaim 35 wherein said latch comprises an inverter having an inputcoupled to said input node and an output coupled to said output node.37. A system as in claim 35 wherein said latch circuit comprises: aninput node for receiving a read signal which renders said latchoperative to determine the voltage at said input node.
 38. A system asin claim 37 wherein said latch circuit further comprises: a first and asecond transistor, each having a source and drain terminal, said firstand second transistors having their source and drain terminal connectedin parallel, said first and second transistors being connected between afirst potential source and said latch input node; a third and a fourthtransistor, each having a source and drain terminal, said third andfourth transistors having their source and drain terminals seriallyconnected, said third and fourth transistors being serially connectedbetween said latch input node and a second potential source; the gatesof said second and fourth transistors being coupled to said output nodeof said latch and the gates of said first and third transistors beingcoupled of said read signal line.
 39. A system as in claim 38 whereinsaid first and second transistors are p-channel transistors and saidthird and fourth transistors are n-channel transistors.
 40. A system asin claim 38 wherein said first and second transistors are coupled tosaid first potential through a fifth transistor, the gate of said fifthtransistor being coupled to a signal line which receives a controlsignal to control the supply of power from said first power source tosaid latch circuit.
 41. A system as in claim 40 further comprising asignal generator for generating said control signal at least during saidread operation.
 42. A system as in claim 33 further comprising: aprogramming circuit for programming said programmable transistor byapplying predetermined voltages to terminals of said programmabletransistor to change said gate threshold voltage from one of said firstand second gate threshold voltages to the other of said first and secondgate threshold voltages.
 43. A system as in claim 42 wherein saidprogramming circuit applies said predetermined voltages to a gate anddrain terminals of said programmable transistor.
 44. A system as inclaim 43 wherein said programmable transistor is an n-channeltransistor.
 45. A system as in claim 33 further comprising: a readsignal generator for generating a read signal, said read circuit beingresponsive to said read signal for determining the operative state ofsaid programmable transistor.
 46. A system as in claim 38 furthercomprising: a read signal generator for generating a read signal on saidread signal line.
 47. A system as in claim 33 wherein a source at saidprogrammable transistor is coupled to said input node, and a drain ofsaid programmable transistor is coupled to a voltage potential when saidthird threshold voltage is applied to said gate terminal.
 48. A methodof operating a programmable circuit, said method comprising: causing agate threshold voltage level of a programmable transistor to be at oneof a first gate threshold voltage value and a second gate thresholdvoltage value; and determining an operative state of said programmabletransistor during a time when said transistor is biased for operationand a third gate threshold voltage, between said first and secondthreshold voltage values, is applied to a gate of said programmabletransistor when said third threshold voltage is applied.
 49. A method asin claim 48 wherein said determining further comprises driving a latchto a predetermined operative state in accordance with the operativestate of said programmable transistor.
 50. A method as in claim 48wherein said determining step occurs in response to the occurrence of aread signal.
 51. A method as in claim 49 wherein said determining stepoccurs in response to the occurrence of a read signal.
 52. A method asin claim 51 further comprising selectively rendering said latchoperative to determine an operative state of said programmabletransistor in response to said read signal.
 53. A method as in claim 48wherein said causing includes programming said programmable transistorby applying predetermined voltages to terminals of said programmabletransistor to change said gate threshold voltage from one of said firstand second gate threshold voltages to the other of said first and secondgate threshold voltages.
 54. A method as in claim 54 wherein saidpredetermined voltages are applied to gate and drain terminals of saidprogrammable transistor.
 55. A method of operating a programmablecircuit comprising: causing the gate threshold voltage of a programmabletransistor to move from one of a first gate threshold voltage and asecond gate threshold voltage to the other of said first gate thresholdvoltage and said second gate threshold voltage by applying predeterminedvoltages to a gate and drain terminal of said programmable transistor.